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Description: this DES made by verilog
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Size: 15360 |
Author: Shawn |
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Description: 16点FFT的VHDL源代码,含详细设计文档。-16:00 FFT of the VHDL source code, including detailed design documents.
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Size: 699392 |
Author: xbl |
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Description: 数据加密算法(Data Encryption Algorithm,DEA)的数据加密标准(Data Encryption Standard,DES)是规范的描述,它出自 IBM 的研究工作,并在 1997 年被美国政府正式采纳。它很可能是使用最广泛的秘钥系统,特别是在保护金融数据的安全中,最初开发的 DES 是嵌入硬 件中的。通常,自动取款机(Automated Teller Machine,ATM)都使用 DES。文件是DES代码的VHDL描述
-Data encryption algorithm (Data Encryption Algorithm, DEA) of the Data Encryption Standard (Data Encryption Standard, DES) is a standardized description of it from IBM s research work and, in 1997, formally adopted by the U.S. government. It is probably the most widely used secret key system, especially in protecting the safety of financial data, the initial development of DES is embedded in hardware. Usually, automated teller machines (Automated Teller Machine, ATM) are the use of DES. Document is described in VHDL code DES
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Size: 676864 |
Author: 陈 |
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Description: Full Des Simulation Code
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Size: 1887232 |
Author: esl |
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Description: DES算法的verilog实现,实现了硬件IC对DES的构架,可以直接应用在系统当中。-DES algorithm Verilog realized, the realization of the hardware IC framework of DES, can be directly used in the system.
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Size: 10240 |
Author: 金鑫 |
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Description: The Data Encryption Standard (DES) is a published federal encryption standard created to protect unclassified computer data and communications. The DES algorithm is the most widely used encryption algorithm in the world
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Size: 1264640 |
Author: sandeep |
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Description: 用VHDL语言实现了DES加密算法,其中包含了测试程序,能够进行仿真。-Using VHDL language implementation of the DES encryption algorithm, which contains the test procedures can be simulated.
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Size: 9216 |
Author: 心飞扬 |
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Description: 有效的改进3-DES算法的执行速度,采用了多级流水线技术,设计了一种高速的硬件结构,使得原来需要48个时钟周期才能完成的运算,现在只需要一个时钟周期就可以完成。另外通过增加输入/输出的控制信号。使得该IP可以方便的集成到SOC中,大大缩短了SOC的设计周期。-Effective 3-DES algorithm to improve the implementation of speed, multi-stage pipeline technology, designed a high-speed hardware architecture, making the original 48 clock cycles required to complete the operation, and now only need one clock cycle can be completed. In addition by increasing the input/output control signal. Makes the IP can be easily integrated into the SOC, the SOC has significantly shortened the design cycle.
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Size: 23552 |
Author: charity |
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Description: High-Speed DES and Triple DES Encryptor Decryptor
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Size: 32768 |
Author: ryan |
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Description: DES-3 VHDL Code implemented on FPGA ,including related document
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Size: 138240 |
Author: VISHWANATH PATEL |
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Description: des开源实现,vhdl文件格式. des 1-des design
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Size: 10240 |
Author: richard |
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Description: des algorithm send rx from serial port
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Size: 3652608 |
Author: mohamed |
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Description: triple des encryption decryption
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Size: 8426496 |
Author: mohamed |
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Description: 3-DES加密IP核VHDL源码,3次DES流水执行-VHDL source code for 3-DES encryption IP core, pipelined execution
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Size: 31744 |
Author: Yan, Like |
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Description: VHDL & Verilog Synthesizable model of the
Data Encryption Standard (DES)
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Size: 47104 |
Author: changjc |
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Description: This is verilog source code for DES(Data Encryption standard) which is used in network security.
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Size: 20480 |
Author: Krupesh |
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Description: Triple DES cipher files
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Size: 141312 |
Author: Abirami Prabhakaran |
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Description: DES加密算法的Verilog HDL实现,带模式选择端口,可以实现加密和解密,已经modelsim仿真通过。-Des En/Decrypt,Verilog HDL code
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Size: 8192 |
Author: Amazing_Eric |
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Description: des encryption with vhdl
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Size: 292864 |
Author: samo |
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Description: DES算法的verilog实现,可以研究下。-DES for Verilog。
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Size: 33792 |
Author: lina |
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